The International Software & Productivity Engineering Institute (INTSPEI) announced that it will partner with the Design, Testing and Formal Verification Techniques for Integrated Circuits and Systems (DTVCS 2008), which will be hosted at the IASTED International Conference on Circuits and Systems (CS 2008) in Kailua-Kona, Hawaii, USA on August 18-20, 2008.

Design, Testing and Formal Verification Techniques for Integrated Circuits and Systems (DTVCS 2008) invites software and hardware engineering researchers, computer scientists and industry luminaries to share theories, new ideas, proven techniques and experiences related to all areas of design, testing and formal verification techniques for integrated circuits and systems.

Topics of interest include, but are not limited to theory and foundations: model checking, SAT-based methods, use of PSL, compositional and probabilistic methods, testing and verification applications and methods, etc. Contributions to UML and formal paradigms based on process algebras, Petri-nets, automaton theory and BDDs in the context of design, testing and formal verification techniques for integrated circuits and systems are also encouraged.

“The integrated circuits and systems industry is continuing to expand and develop quickly,” said the DTVCS 2008 chairman, Dr. Ka Lok Man. “The DTVCS 2008 aims to gather all interested researchers and practitioners to exchange ideas and to understand developmental and investigational trends.”

“We are happy to support DTVCS 2008,” said Dr. Anatoliy Doroshenko, Research Director of INTSPEI. “We are sure that the support of scientific conferences and events will help us better communicate our vision to the professional environment and expedite the development of the IT field.”